Technical Field
The disclosure in generally relates to a semiconductor integrated circuit (IC) and the applications thereof, and more particularly to an electrostatic discharge (ESD) protection apparatus and the applications thereof.
Description of the Related Art
An ESD event commonly results from the discharge of a high voltage potential and leads to pulses of high current in a short duration (typically, 100 nanoseconds). Semiconductor IC is vulnerable to ESD events resulted by human contact with the leads of the IC or electrically charged machinery being discharged in other leads of the IC. Accordingly, an ESD protection circuit is essential to a semiconductor IC.
A parasitic silicon controlled rectifier (SCR) is one kind of on-chip semiconductor ESD protection device. Due to its high current sinking/sourcing capability, very low turn-on impedance, low power dissipation, and large physical volume for heat dissipating, parasitic lateral SCR devices have been recognized in the prior art as one of the most effective elements in semiconductor ESD protection circuits.
However, there is a major disadvantage with using the parasitic SCR in ESD protection circuits, the parasitic SCR has a holding voltage far less than its trigger voltage. For example, the holding voltage of a typical parasitic SCR device is about 3.6V. Once the parasitic SCR is triggered under a high-voltage operation (the operation voltage is high than 20V), electrical overstress (EOS) or latch up risk may occur during a subsequent normal operation (the operation voltage is about 2V). In order to reduce the EOS or latch up risk, a conventional approach is applied to increase holding voltage of the parasitic SCR by elongating the distance between the anode and the cathode of the parasitic SCR. But, by this approach, the lay-out size of the semiconductor IC can be increased which does not caught up with the design trends toward scaling down the size of the semiconductor device.
Therefore, there is a need of providing an improved ESD protection apparatus and the applications thereof to obviate the drawbacks encountered from the prior art.